This disclosure relates to semiconductor memory devices, and more particularly, to a nonvolatile memory device including a sudden power off detection circuit.
A semiconductor memory device is classified into a volatile memory device and a nonvolatile memory device. A volatile memory device has a high read/write speed but loses its stored data when its power is interrupted. A nonvolatile memory device retains its stored data even when its power is interrupted. Thus, a nonvolatile memory device is used to store data that should be preserved regardless of whether or not a power is supplied.
A semiconductor memory device is supplied with power from an internal or external power supply. If power is suddenly cut off from the power supply (hereinafter this is referred to as a sudden power off), a fatal defect such as data being erroneously programmed in a semiconductor memory device may occur. As a result of the sudden power off, the semiconductor memory device may be damaged.
Various technical methods for solving problems due to the sudden power off have been suggested. To correctly apply those technical methods, when a sudden power off occurs, a sudden power off detection circuit (hereinafter it is referred to as a SPO detection circuit) for sensing the sudden power off may be used. To improve performance of the semiconductor memory device, there is a growing need for developing a more effective sudden power off detection circuit.